1. Field of the Invention
The present invention relates to substrate potential generation circuits, and more particularly, to a structure of a circuit for controlling a substrate bias potential within a predetermined voltage range required for an integrated circuit device such as a semiconductor memory.
2. Description of the Background Art
The source and drain regions of an MOSFET forming an integrated circuit such as a semiconductor memory form a pn junction with the substrate to have a junction capacitance that cannot be neglected in the circuit operation. This junction capacitance becomes the cause of degrading the operation rate of circuitry. The pn junction capacitance can be reduced in proportion to an applied bias in a reverse direction.
Furthermore, under shooting of noise and external signals such as under shooting of the potential of an n.sup.+ drain region of an MOSFET causes a pn junction to be biased in the forward direction, whereby a small amount of carriers are introduced into the substrate. This introduction of carriers induce the possibility of latch up of a COOS circuit and damage of data stored in a memory cell in a DRAM.
An internal circuit that intentionally applies a reverse bias to the substrate is typically incorporated to solve such a problem.
FIG. 18 is a circuit diagram showing a structure of a conventional substrate potential generation circuit. Referring to FIG. 18, the substrate potential generation circuit mainly includes a substrate potential level detection circuit 100, an oscillator circuit 200, and a charge pump circuit 300.
In substrate potential level detection circuit 100, a p channel MOSFET 102 operating as a current source is connected to a substrate via diode-connected n channel MOSFETs 106 and 108 connected in series to each other, and an n channel MOSFET 104 connected in series to MOSFETs 106 and 108 and having its gate grounded.
When the threshold voltage of n channel MOSFETs 104, 106 and 108 is V.sub.thn, the potential difference across the gate and source of n channel MOSFET 104 is: EQU .vertline.V.sub.o .vertline.=.vertline.V.sub.BB +2V.sub.thn .vertline.(1)
where V.sub.BB is a negative value. When substrate potential V.sub.BB is sufficiently low and .vertline.V.sub.o .vertline. is greater than the threshold voltage of n channel MOSFET 104, n channel MOSFET 104 attains an ON state, and the potential of a node n1 attains an L (Logical Low) level.
Conversely, when substrate bias potential V.sub.BB is high and potential difference .vertline.V.sub.o .vertline. is smaller than threshold voltage V.sub.thn of n channel MOSFET 104, n channel MOSFET 104 is cut off. In this case, the potential of node n1 is pulled up to an H (Logical High) level by the potential supplied from p channel MOSFET 102 which is ON.
More specifically, substrate potential level detection circuit 100 provides a signal of an L level and an H level to node nl when the level of substrate bias potential V.sub.BB is lower and higher, respectively, than a predetermined potential level (in this case, -3.times.V.sub.thn).
The potential of node n1 is applied to one input terminal of an NAND circuit 202 in oscillator circuit 200. The output of NAND circuit 202 is applied to the other input terminal of NAND circuit 202 via a series of an even number of stages of inverters 204, 206, . . . , 208.
Therefore, when the potential of node nl attains an L level, the potential of a node n2 which is the output of NAND circuit 202 is fixed to an H level, so that oscillation does not occur. That is to say, the substrate potential generation circuit is "inactive".
When the substrate bias potential V.sub.BB rises and the potential of node nl is pulled up to an H level, oscillator circuit 200 is activated to initiate oscillation, whereby charge pump circuit 200 is driven. In other words, the substrate potential generation circuit is "active", whereby substrate bias potential V.sub.BB begins to be lowered.
According to the above-described operation, the substrate bias potential is maintained at a predetermined potential.
The structure of the above-described substrate potential generation circuit is not sufficient by reasons set forth in the following when the substrate potential is greatly shifted to the negative side than the predetermined potential due to variation of the power supply potential.
When the substrate potential is shifted towards the negative side, the time constant T for that potential to be restored is T=R.multidot.C which is the product of capacitance C of a substrate and impedance R of a substrate. The value of the substrate impedance is generally great since it is determined by leakage current or the like of the pn junction formed at the substrate. This means that time constant T is also increased to result in a longer time period for the substrate potential to be restored.
Variation of the substrate potential will affect the threshold voltage of each transistor formed on the same substrate. It will directly influence the circuit operation characteristics, such as the operation margin. If the time required for the substrate potential to attain the stable state after variation is appreciable, the operation of each element formed on a substrate will become unstable.
A conventional substrate potential clamp circuit 400 for addressing this problem is shown in FIG. 19.
Referring to FIG. 19, a plurality of diode-connected n channel MOSFETs 402-408 are connected in series. These MOSFETs serve to couple the substrate with the ground potential. When the substrate potential become lower than -4.times.V.sub.thn where V.sub.thn is the threshold voltage of an n channel MOSFET, the substrate is connected to ground, whereby the substrate potential is pulled up. More specifically, the substrate potential greatly shifted towards the negative side is restored to V.sub.BB =-4.times.V.sub.thn at a short time constant. Thus, this circuit includes the clamping function to suppress the absolute value of the substrate potential from exceeding 4.times.V.sub.thn.
Since the substrate potential directly affects the operation characteristics of circuitry, a stable value must be constantly maintained. It is necessary that the substrate potential generation circuit operates even during stand-by. In other words, power consumption of the substrate potential generation circuit is an important factor that determines the power consumption of the entire circuit during stand-by.
Particular attention must be paid in the case where a DRAM incorporated in a substrate potential generation circuit is operated by a battery.
In the substrate potential generation circuit of FIG. 18, oscillator circuit 200 consumes the greatest power. FIG. 20 shows a detail circuit diagram thereof.
At the first stage, a NAND circuit 202 receiving an output signal out4 of substrate potential detection circuit 100 (FIG. 18) is provided. A ring oscillator circuit is formed with an even number of stages of CMOS inverters connected.
The conventional substrate potential generation circuit of the above-described structure has problems set forth in the following.
Firstly, there was a problem that the power supply voltage dependency of the pull up current is great since p channel MOS transistor 102 having its gate potential grounded is used as the current supply circuit of the pull up side in substrate potential level detection circuit 100.
When the power supply voltage is increased to result in a greater pull up current, the level of the substrate potential at which oscillation circuit operation control signal out4, from substrate potential level detection circuit 100, switches becomes lower. Therefore, the absolute value of substrate potential V.sub.BB is increased together with the rise of the power supply voltage as shown by the dotted line of FIG. 17(A).
Secondly, the absolute value of the potential that causes switching of oscillation circuit operation control signal out4 (referred to as predetermined potential hereinafter) is reduced since the threshold voltage of the MOSFET determining the predetermined potential becomes lower in proportion to a rise in temperature. Therefore, the absolute value of the substrate potential controlled by the substrate potential generation circuit is reduced as the temperature becomes higher as shown in the dotted line in FIG. 17(B).
The third problem is that the operation of clamping the potential is too slow. This is because the current value flowing through the conventional clamp circuit changes its level in a relatively slow manner in the proximity of the threshold voltage at which a clamping operation is initiated when the substrate potential is greatly shifted towards the negative stop side than the predetermined potential. Control by the conventional clamp circuit is only effective when the difference between the predetermined potential and substrate potential is sufficient.
Thus, the conventional substrate potential generation circuit has the disadvantage that the controllability is poor with respect to variation in the external environment and external operation condition according to the above-described three points.
Fourthly, power consumption of the circuitry incorporating ring oscillator 200 is increased during stand-by since ring oscillator 200 consumes a great amount of current. Therefore, the operation margin is limited by external operation conditions such as the power source, or the operating condition of the mounted circuit is limited.